legal disclaimer notice rev 1 . nov . 20 10 LT4953C parameter symbol limit unit drainsource voltage v dss 30 v gatesource voltage v gss 20 v t a =25 5.3 continuous drain current(tj=150 ) t a =70 i d 4.3 a pulsed drain current i dm 30 a continuous source current (diode conduction) i s 1.7 a t a =25 2.0 maximum power dissipation t a =70 p d 1.3 w operating junction temperature t j 55 to 150 storage temperature range t stg 55 to 150 tQ10 sec 47 thermal resistancejunction to ambient * r ja steady state 75 /w thermal resistancejunction to case r jc 45 /w general description the LT4953C is the dual pchannel logic enhancement mode power field effect transistors are produced using high ce ll density, dmos trench technology. this high density process is esp ecially tailored to minimize onstate resistance. these devices are par ticularly suited for low voltage application such as cellular phone and notebook computer power management and low inline power los s are needed in a very small outline surface mount package. features r ds(on) Q 60m@v gs =10v r ds(on) Q 90m@v gs =4.5v super high density cell design for extremely low r ds(on) exceptional onresistance and maximum dc current capability applications power management in note book portable equipment battery powered system dc/dc converter load switch dsc lcd display inverter pin configuration absolute maximum ratings (t a =25 unless otherwise noted) (sop8) top view *the device mounted on 1in 2 fr4 board with 2 oz copper ordering information : LT4953C (pbfree)
legal disclaimer notice rev 1 . nov . 20 10 LT4953C symbol parameter limit min typ max unit static v gs(th) gate threshold voltage v ds =v gs , i d =250 a 1 1.4 3 v i gss gate leakage current v ds =0v, v gs =20v 100 na v ds =30v, v gs =0v 1 i dss zero gate voltage drain current v ds =30v, v gs =0v t j =55 25 a v gs =10v, i d = 5.3a 50 60 r ds(on) drainsource onresistance v gs =4.5v, i d = 4.2a 69 90 m v sd diode forward voltage i s =1.7a, v gs =0v 0.8 1.2 v dynamic rg gate resistance v ds =0v, v gs =0v, f=1mhz 3.5 ciss input capacitance 450 490 coss output capacitance 70 crss reverse transfer capacitance v ds =15v, v gs =0v, f=1.0mhz 20 pf qg total gate charge 14 17 qgs gatesource charge 4 qgd gatedrain charge v ds =15v, v gs =10v, i d =5.3a 3 nc t d(on) turnon delay time 27 33 tr turnon rise time 11 15 t d(off) turnoff delay time 40 52 t f turnoff fall time v dd =15v, r l =15 i d =1.0a, v gen =10v r g =6 4 6 ns notes: a. pulse test; pulse width Q 300us, duty cycle Q 2% electrical characteristics (t a =25 unless otherwise specified)
legal disclaimer notice rev 1 . nov . 20 10 LT4953C typical characteristics (t j =25 noted)
legal disclaimer notice rev 1 . nov . 20 10 LT4953C typical characteristics (t j =25 noted)
legal disclaimer notice rev 1 . nov . 20 10 LT4953C sop-8 package outline notes: 1. pkg all surfaces are ra0.8-1.2um. 2. mold flash, protrusions or gate burrs shall not exceed 0.15 mm in total (both sides).
legal disclaimer notice rev 1 . nov . 20 10 LT4953C important notice and disclaimer lsc reserves the right to make changes to this docu ment and its products and specifications at any time without notice. customers should obtain an d confirm the latest product information and specifications before final design, purchase or use . lsc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does lsc assume any liabili ty for application assistance or customer product design. lsc does not warrant or accept any liability with products which are purchased or used for any unintended or unauthorized application . no license is granted by implication or otherwise u nder any intellectual property rights of lsc. lsc products are not authorized for use as critical components in life support devices or systems without express written approval of lsc.
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